This invention relates to a nonvolatile semiconductor memory device, and more particularly, to a NAND flash memory which can perform a data rewriting operation (write and erase operation).
Conventionally, a NAND flash memory is well known as a nonvolatile semiconductor memory device which can be subjected to an electrical data rewriting operation and suitably formed with high integration density and large capacity (increase in memory capacity).
Recently, the integration density of the NAND flash memory has been further increased with the improvement of the memory cell structure and the development of a fine patterning technique. Further, it is strongly required to increase the operation speed with an increase in the memory capacity.
However, in the recent NAND flash memory, the width of and the interval between word lines have been made small with the development of the fine patterning technique. Likewise, the width of and the interval between bit lines have also been made small. Therefore, the resistances of the word lines and bit lines have become larger; the coupling capacitances between word lines, between bit lines, and between word lines and bit lines have become large; and the influence of coupling noise has become large.
Further, in the recent NAND flash memory, peak currents during the read operation and verification operation become larger with an increase in the number of memory cells for each word line. As a method for reducing the peak currents, it is considered to separately perform the read and verification operations a plurality of times (for example, twice). However, in the case of this method, when the potential of a bit line which is first subjected to the read and verification operations is discharged (conducting cell), the potential of the word line fluctuates because of the coupling between the word line and the bit line. In this case, the next read and verification operations cannot be started until the potential of the word line returns to a preset value. The fluctuation in the potential of the word line becomes larger with an increase in the coupling capacitance between the word line and the bit line. That is, since the time length until the potential returns to the preset value becomes larger if the fluctuation in the potential of the word line becomes larger, there occurs a problem that the read and verification operations are delayed.
A NAND flash memory in which page buffers are divisionally driven is already proposed (for example, refer to U.S. Patent Specification No. 2006/0104125 A1).